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Communication Dans Un Congrès Année : 2023

A Scalable low-latency FPGA architecture forSpin qubit control through direct digital synthesis

Résumé

Scaling qubit control is a key issue for Large Scale Quantum (LSQ) computing and hardware control systems are increasingly costly in logic and memory resources. We present a newly developed compact Direct Digital Synthesis (DDS) architecture for signal generation for spin qubits that is scalable in terms of waveform accuracy and the number of synchronized channels. Fine control of gate voltages is achieved by on-the-fly generation of very precise ramps. Embedded memory requirements are reduced by orders of magnitude compared to current Arbitrary Waveform Generator (AWG) architectures, removing a major scalability barrier for quantum computing.
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Dates et versions

cea-04600892 , version 1 (04-06-2024)

Identifiants

  • HAL Id : cea-04600892 , version 1

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Mathieu Toubeix, Eric Guthmuller, Adrian Evans, Tristan Meunier. A Scalable low-latency FPGA architecture forSpin qubit control through direct digital synthesis. DATE 2024 - Design, Automation and Test in Europe Conference, Mar 2024, Valence, Spain. ⟨cea-04600892⟩
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